**Revision**: V0.1 – Draft **Prepared By**: 1775 West Hibiscus Blvd., Suite 200 Melbourne FL 32901 (321) 984‑1671 **Applicable Data Rights Statement**: AERONIX PROPRIETARY ‑ COMPETITION SENSITIVE. --- # Table of Contents | # | Section | Page | |---|---------|------| | 1 | **SCOPE** | 1 | | 2 | **Referenced Documents** | 2 | | 3 | **Test Execution and Recording** | 3 | | 3.1 | Datasheet Reporting | 3 | | 3.2 | Test Equipment | 3 | | 4 | **Procedure** | 4 | | 4.1 | Visual Inspection | 4 | | 4.2 | Electrical Continuity & Shorts | 5 | | 4.3 | Power System Tests | 6 | | 4.4 | Functional Tests | 8 | | 4.5 | Environmental / Stress Tests | 12 | | A | **Test Datasheet** | 14 | --- ## 1. SCOPE This test plan validates the **LoRa Car Radio Evaluation Board** (design reference AE104193‑001 Rev V2) in accordance with the PCB Manual requirements. The plan covers visual inspection, electrical continuity/short‑circuit checks, power‑rail verification, functional verification of major subsystems (MCU, USB debug port, LoRa radio, external I/O header, power‑monitoring), and a placeholder environmental‑stress sequence. --- ## 2. Referenced Documents | Ref No. | Document | Revision | Page | |---------|----------|----------|------| | 2‑1 | PCB Manual – AE104193‑001 | V2 | 1‑9 | | 2‑2 | Component Datasheets (SX1276, NCP1117, LP2985‑33, ATMEGA328P, etc.) | latest | – | | 2‑3 | IPC‑610 Class 2 Visual‑Inspection Standard | 2023 | – | | 2‑4 | IEC 60730‑1 (Environmental Test Guidelines) | 2022 | – | | 2‑5 | Test Equipment Calibration Certificates | – | – | --- ## 3. Test Execution and Recording ### 3.1 Datasheet Reporting All measured values shall be recorded on the **Test Datasheet** (Appendix A). For each test case record: * **Actual Result** – numeric value or observation. * **Pass/Fail (P/F)** – “P” if within tolerance, “F” otherwise. If a test does not apply to a particular board revision, mark **N/A**. ### 3.2 Test Equipment | Item # | Equipment | Model / Spec | Calibration Due | |--------|-----------|--------------|-----------------| | 1 | DC Power Supply (programmable) | Keysight E36313A, 0‑5 V, 1 A | 12 months | | 2 | Digital Multimeter (continuity/voltage) | Fluke 8845A | 12 months | | 3 | 4‑Channel Oscilloscope | Tektronix MDO3014, 350 MHz | 12 months | | 4 | USB‑to‑UART Bridge | FTDI FT232RL | 12 months | | 5 | JTAG / SWD Programmer | Segger J‑Link JTAG | 12 months | | 6 | USB 2.0 Host PC (Windows 10) | – | – | | 7 | Temperature Chamber (optional) | – | – | | 8 | X‑Y Table for visual inspection | – | – | | 9 | Magnification Lamp (≥ 30×) | – | – | | 10 | ESD‑safe workstation with wrist strap | – | – | --- ## 4. Procedure > **NOTE** – The procedure must be executed in the order presented. A failure at any step requires corrective action and a **re‑run from the beginning** of the procedure. ### 4.1 Visual Inspection | **Test‑ID** | **Description** | **Acceptance Criteria (Expected Result)** | **Actual Result** | **Pass/Fail** | |------------|-----------------|--------------------------------------------|-------------------|---------------| | V‑001 | Verify that the board is clean, free of flux residues, and conforms to IPC‑610 Class 2. | No visible solder balls, splatter, or residues; surface free of scratches. | | | | V‑002 | Confirm component polarity and orientation for all polarized devices (U1 NCP1117, U2 LP2985‑33, diodes D2/D3, electrolytic C1‑C4, LEDs). | All polarized parts aligned with silkscreen arrows/marks. | | | | V‑003 | Check that all IC footprints match the installed parts (package, pin count). | Footprint‑to‑device match for every component listed in BOM. | | | | V‑004 | Inspect silkscreen for missing or erroneous reference designators, especially for the external I/O header (P2) pinout. | All reference designators present, legible, and correctly placed. | | | | V‑005 | Verify that the barrel‑type power jack (J3) is soldered correctly (no lifted pads, correct polarity marking). | Jack firmly soldered, pins aligned, polarity marking correct (+5 V on pin 1). | | | | V‑006 | Confirm that the SMA connectors for LoRa antenna (J5) and GPS antenna (J6) are fully seated and mechanically secured. | No visible gaps; locking nuts (if any) tightened. | | | | V‑007 | Check that the 2‑row 100 mil external I/O header (J2) has correct row assignment (signal row vs. GND row). | Signal pins on row 1, dedicated GND pins on row 2, per manual. | | | | V‑008 | Verify presence and correct placement of fiducials (FD1‑FD3) for assembly alignment. | Fiducials present, shape and location as per design. | | | | V‑009 | Examine the PCB for any mechanical damage (cracks, delamination) after handling. | No damage observed. | | | --- ### 4.2 Electrical Continuity & Shorts | **Test‑ID** | **Description** | **Expected Result** | **Actual Result** | **Pass/Fail** | |------------|-----------------|---------------------|-------------------|---------------| | C‑001 | Continuity from **Barrel‑Jack GND (J3‑2)** to **Ground Pad TP2** and to **All GND pins on the external I/O header**. | ≤ 0.1 Ω resistance (continuous). | | | | C‑002 | Verify that **Barrel‑Jack +5 V (J3‑1)** is **not** shorted to GND, any RF pins, or the 3.3 V rail (U6‑14‑16). | Open circuit (∞ Ω). | | | | C‑003 | Check that **3.3 V rail (TP1 – VCC_3V3)** is isolated from **+5 V rail**. | Open circuit. | | | | C‑004 | Continuity of **+5 V rail** from **Barrel‑Jack** to **Power IC U2 (VOUT)** and to **Power Monitoring ADC pin (TP5)**. | ≤ 0.1 Ω. | | | | C‑005 | Verify that **LoRa RF input SMA (J5)** and **GPS SMA (J6)** are not shorted to any DC rails. | Open circuit. | | | | C‑006 | Continuity of **I²C bus**: SDA (TP3 – U1_I2C_SDA) to **Header Pin P2‑7**, SCL (TP4) to **Header Pin P2‑8**. | ≤ 0.1 Ω. | | | | C‑007 | Check that **UART TX (TP10)** and **UART RX (TP11)** are correctly routed to the USB‑to‑UART bridge pins (no shorts). | Open between TX and RX; continuity to respective pins. | | | | C‑008 | Verify that **SPI pins** (MOSI, MISO, SCK, CS) are isolated from each other when not driven. | Open between each pair (≥ 10 MΩ). | | | | C‑009 | Confirm that **DAC output pins** are not shorted to ground. | Open circuit. | | | | C‑010 | Verify that **Battery‑Power Switchover MOSFET (T1 – FDN340P)** source‑drain are not shorted when un‑biased. | Open circuit. | | | --- ### 4.3 Power System Tests #### 4.3.1 Voltage‑Rail Verification | **Test‑ID** | **Description** | **Target Voltage / Tolerance** | **Actual Result** | **Pass/Fail** | |------------|-----------------|-------------------------------|-------------------|---------------| | P‑001 | Measure **+5 V rail** at **Barrel‑Jack (J3‑1)** with no load. | 5.00 V ± 0.05 V | | | | P‑002 | Measure **+5 V rail** at **U2 (LP2985‑33) VOUT** under nominal load (≈ 150 mA). | 5.00 V ± 0.05 V | | | | P‑003 | Measure **+3.3 V rail** (TP1) after regulation by **U1 (NCP1117)** under full‑board load. | 3.30 V ± 0.05 V | | | | P‑004 | Measure **+3.3 V_RF** (U12‑1) that powers the LoRa front‑end. | 3.30 V ± 0.05 V | | | | P‑005 | Verify **USB‑VCC (5 V)** on USB‑B connector (J1) when board is powered from barrel jack. | 5.00 V ± 0.05 V | | | | P‑006 | Verify **Battery voltage** at **BAT_TP** (if present) when a 3.7 V Li‑ion cell is connected. | 3.6 V ± 0.2 V (no load) | | | | P‑007 | Confirm **No‑load current draw** from the barrel jack. | ≤ 30 mA | | | | P‑008 | Verify **Maximum steady‑state current** with all primary subsystems enabled (LoRa TX at 20 dBm, Ethernet active, USB debugging). | ≤ 200 mA (per manual) | | | | P‑009 | Check **Power‑monitoring ADC reading** (via I²C register) matches measured rail voltage (±2 %). | ADC value within ±2 % of multimeter reading. | | | | P‑010 | Verify **Hot‑swap behavior**: connect/disconnect barrel jack while the board is powered from battery; observe no brown‑out on MCU. | MCU remains in run mode, voltage on VCC_3V3 stays > 3.0 V. | | | | P‑011 | Verify **Charging current** when a Li‑ion cell is attached and barrel jack is powered: charging current ≤ 500 mA and voltage rise follows charging profile. | Charging current 300‑500 mA, battery voltage increases. | | | #### 4.3.2 Oscilloscope Checks | **Test‑ID** | **Description** | **Expected Waveform / Parameter** | **Actual Result** | **Pass/Fail** | |------------|-----------------|-----------------------------------|-------------------|---------------| | P‑012 | Probe **U1 CLK_OUT** (16 MHz crystal Y1) – frequency & duty cycle. | 16.00 MHz ± 0.5 %, 50 % ± 5 % duty. | | | | P‑013 | Probe **LoRa DIO0** interrupt line when a known packet is transmitted. | Clean rising edge within 1 µs of packet end. | | | | P‑014 | Probe **USB‑D+ / D‑** idle state (should be SE0 when not enumerated). | Both lines at 0 V (SE0) for ≥ 2 ms. | | | | P‑015 | Verify **1 PPS** output from GPS module (if present) – 1 Hz square wave, 5 V TTL. | 1 Hz, 0 V–5 V, 50 % duty. | | | --- ### 4.4 Functional Tests | **Test‑ID** | **Description** | **Procedure Summary** | **Expected Result** | **Actual Result** | **Pass/Fail** | |------------|-----------------|-----------------------|---------------------|-------------------|---------------| | F‑001 | **MCU Boot & UART Debug** – Power up board, open UART (115200‑8‑N‑1). | Reset via SW1, monitor console. | “Bootloader ready” message appears within 2 s. | | | | F‑002 | **Firmware Programming** – Load test firmware via JTAG. | Use Segger J‑Link, flash image “car_radio_demo.bin”. | Programming completes, verification passes (checksum OK). | | | | F‑003 | **GPIO Toggle Test** – Verify all 8 GPIO pins on external header. | Send command `gpio set <0|1>` via UART; read back state. | Pin state matches command; no cross‑talk. | | | | F‑004 | **ADC Measurement** – Read two ADC channels (TP‑ADC0, TP‑ADC1). | Apply known voltages (0 V, 1.65 V) to test points, request ADC read. | ADC values within ±2 % of applied voltage. | | | | F‑005 | **DAC Output Test** – Output known codes, measure voltage. | Write DAC code 0x00, 0x80, 0xFF via I²C; measure with multimeter. | 0 V, ≈ 1.65 V, ≈ 3.30 V respectively (±5 %). | | | | F‑006 | **I²C Bus Scan** – Verify that all expected slave addresses are present. | Issue I²C scan command. | Addresses for power‑monitor IC, EEPROM, LoRa radio (0x68, 0x50, 0x60) returned. | | | | F‑007 | **SPI Loopback Test** – Verify SPI master (MCU) communication. | Connect MOSI ↔ MISO via test jumper, send pattern 0xA5A5, read back. | Received pattern matches transmitted. | | | | F‑008 | **LoRa Transmit/Receive** – Simple point‑to‑point test between two boards. | Configure both boards to same frequency (868 MHz), SF7, BW125 kHz; send “HELLO”. | Receiving board reports correct payload, RSSI within spec. | | | | F‑009 | **Ethernet Link Test** (Base‑Station variant only – placeholder). | Connect RJ45 to switch, verify link LED, ping board IP. | Link LED solid, ping reply < 5 ms. | N/A (Car‑Radio) | | | F‑010 | **USB Debug Port** – Verify enumeration as CDC‑ACM device. | Connect USB‑B to PC, check Device Manager. | Device appears as “USB Serial Device”, COM port created. | | | | F‑011 | **Power‑Monitoring API** – Read battery level and total board current. | Issue command `pm read` over UART. | Returns battery voltage ~3.7 V, current ≈ 120 mA. | | | | F‑012 | **Hot‑Swap Continuity** – Power off barrel jack while board runs on battery, then re‑apply. | Observe UART console for “POWER SWITCH TO EXTERNAL” message, no reset. | Message displayed, MCU stays in run mode. | | | | F‑013 | **Safety – Over‑Current Protection** – Force over‑current (> 250 mA) and verify supply shuts down. | Set power supply limit to 250 mA, short a load briefly. | Supply enters CC mode, board voltage collapses, then recovers when limit raised. | | | | F‑014 | **GPS 1PPS Integration** (if GPS module populated). | Enable GPS, monitor 1PPS line with oscilloscope while board is powered. | Stable 1 Hz pulse, MCU timestamps align within ±10 µs. | N/A (optional) |